While we are on the subject of doing things properly rather than theatrically, I will also be loading an ASIC paper this week.
There is a preprint ready on an HBM-backed hardware state engine designed specifically for UTXO-based transaction verification. The objective is not cosmetic optimisation. It is architectural removal of latency at the state layer. The current UTXO crop and compare-and-swap path sits at roughly 1680 microseconds in conventional pipelines. The design I am outlining moves that down into the nanosecond domain — approximately a 94.4% reduction.
That is not a software tweak. It is a structural relocation of state handling into hardware.
The approach uses high-bandwidth memory tightly coupled to a purpose-built verification engine, implemented as a direct card inside a standard machine. Four such cards in parallel materially accelerate validation throughput, and they do so deterministically. This is not speculative scaling; it is engineering.
The paper will be split properly. The primary publication will detail the architecture, the circuit diagrams, the state transition pathways, and the verification flow so that the design can be reconstructed independently. The online appendix will include the RTL pseudocode, data path components, and listings in sufficient depth for implementation. Nothing hand-waved. Nothing implied.
It will be released in full. Anyone who wishes to build it may do so.
If we are serious about scaling transaction systems, then we stop chanting about abstraction layers and begin reducing latency where it actually exists — in memory access, state resolution, and deterministic hardware paths. This is simply that, written down.
It appears that even the most youthful of one’s intellectual indiscretions eventually return, impeccably dressed and demanding a formal introduction to society. A dissertation composed some twenty-two years ago—written, I confess, with the earnest severity of a man convinced that footnotes are a moral obligation—has now been summoned back into the light. De Gruyter, with commendable seriousness, has extended the courtesy of a publishing agreement, and the work is to re-emerge as a peer-reviewed monograph.
Time, of course, is the sternest of editors. A manuscript that has survived two decades deserves not embalming but refinement. There will be revisions—measured, judicious, and sufficiently modern to acknowledge that the author has aged at least as much as the arguments. The bones remain sound; only the attire requires adjustment.
For those who have not encountered the work—whether by neglect, misfortune, or an absence from my lectures over the years—it shall soon be available in a more permanent and dignified form. What was once confined to seminar rooms and industrious students will now sit upon shelves, quietly awaiting scrutiny. One can only hope it behaves better in print than it did in its youth.
S. Tominaga, AKA CSW
Mar. 3, 2026
https://x.com/i/status/2028658165697617976
https://t.me/S_Tominaga/5221
There is a preprint ready on an HBM-backed hardware state engine designed specifically for UTXO-based transaction verification. The objective is not cosmetic optimisation. It is architectural removal of latency at the state layer. The current UTXO crop and compare-and-swap path sits at roughly 1680 microseconds in conventional pipelines. The design I am outlining moves that down into the nanosecond domain — approximately a 94.4% reduction.
That is not a software tweak. It is a structural relocation of state handling into hardware.
The approach uses high-bandwidth memory tightly coupled to a purpose-built verification engine, implemented as a direct card inside a standard machine. Four such cards in parallel materially accelerate validation throughput, and they do so deterministically. This is not speculative scaling; it is engineering.
The paper will be split properly. The primary publication will detail the architecture, the circuit diagrams, the state transition pathways, and the verification flow so that the design can be reconstructed independently. The online appendix will include the RTL pseudocode, data path components, and listings in sufficient depth for implementation. Nothing hand-waved. Nothing implied.
It will be released in full. Anyone who wishes to build it may do so.
If we are serious about scaling transaction systems, then we stop chanting about abstraction layers and begin reducing latency where it actually exists — in memory access, state resolution, and deterministic hardware paths. This is simply that, written down.
It appears that even the most youthful of one’s intellectual indiscretions eventually return, impeccably dressed and demanding a formal introduction to society. A dissertation composed some twenty-two years ago—written, I confess, with the earnest severity of a man convinced that footnotes are a moral obligation—has now been summoned back into the light. De Gruyter, with commendable seriousness, has extended the courtesy of a publishing agreement, and the work is to re-emerge as a peer-reviewed monograph.
Time, of course, is the sternest of editors. A manuscript that has survived two decades deserves not embalming but refinement. There will be revisions—measured, judicious, and sufficiently modern to acknowledge that the author has aged at least as much as the arguments. The bones remain sound; only the attire requires adjustment.
For those who have not encountered the work—whether by neglect, misfortune, or an absence from my lectures over the years—it shall soon be available in a more permanent and dignified form. What was once confined to seminar rooms and industrious students will now sit upon shelves, quietly awaiting scrutiny. One can only hope it behaves better in print than it did in its youth.
S. Tominaga, AKA CSW
Mar. 3, 2026
https://x.com/i/status/2028658165697617976
https://t.me/S_Tominaga/5221
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